/* data structures which describe registers on the American Micro Circuits Corporation (AMCC) “matchmaker” S5933Q PCI bridge chip on the Applied Telecom OC12c/OC3c ATM/PPP PCI network interface card (NIC) Note 1: these data structures use bit fields, which are compiler- and Central Processing Unit (CPU) specific, so you will probably have to rewrite these data structures if you port to another CPU or compiler On the Intel CPU’s using the Borland C++ 4.5 compiler, bits are assigned from least significant to most significant within a word, and less significant bytes of a word are stored at lower memory addresses No padding is inserted, and bitfields can straddle word boundaries The width of each bitfield must be from 1 to 16 (see page 62 of the Borland C++ version 4.5 Programmer’s Guide). Note 2: due to the use of anonymous unions, this header can only be included from C++ code, not C code Note 3: definitions of readability/writability abbreviations: W/O writable only R/O readable only W/R writable and readable CW/R readable, but writable only after CWRE bit set in Control_register Note 4: definition of perspective of read transfers read a transfer from PCI bus to addon bus write a transfer from addon bus to PCI bus */ #ifndef _AMCC_H #define _AMCC_H #include “../types/types.h” struct AmccMailBoxStatuses_register { // bit is 1 if corresponding byte of corresponding mailbox // has been written by PCI bus, but not read by add-on bus // Bit32 OutgoingMailBox1Byte0Full : 1; Bit32 OutgoingMailBox1Byte1Full : 1; Bit32 OutgoingMailBox1Byte2Full : 1; Bit32 OutgoingMailBox1Byte3Full : 1; Bit32 OutgoingMailBox2Byte0Full : 1; Bit32 OutgoingMailBox2Byte1Full : 1; Bit32 OutgoingMailBox2Byte2Full : 1; Bit32 OutgoingMailBox2Byte3Full : 1; Bit32 OutgoingMailBox3Byte0Full : 1; Bit32 OutgoingMailBox3Byte1Full : 1; Bit32 OutgoingMailBox3Byte2Full : 1; Bit32 OutgoingMailBox3Byte3Full : 1; Bit32 OutgoingMailBox4Byte0Full : 1; Bit32 OutgoingMailBox4Byte1Full : 1; Bit32 OutgoingMailBox4Byte2Full : 1; Bit32 OutgoingMailBox4Byte3Full : 1; // bit is 1 if corresponding byte of corresponding mailbox // has been written by add-on bus, but not read by PCI bus // Bit32 IncomingMailBox1Byte0Full : 1; Bit32 IncomingMailBox1Byte1Full : 1; Bit32 IncomingMailBox1Byte2Full : 1; Bit32 IncomingMailBox1Byte3Full : 1; Bit32 IncomingMailBox2Byte0Full : 1; Bit32 IncomingMailBox2Byte1Full : 1; Bit32 IncomingMailBox2Byte2Full : 1; Bit32 IncomingMailBox2Byte3Full : 1; Bit32 IncomingMailBox3Byte0Full : 1; Bit32 IncomingMailBox3Byte1Full : 1; Bit32 IncomingMailBox3Byte2Full : 1; Bit32 IncomingMailBox3Byte3Full : 1; Bit32 IncomingMailBox4Byte0Full : 1; Bit32 IncomingMailBox4Byte1Full : 1; Bit32 IncomingMailBox4Byte2Full : 1; Bit32 IncomingMailBox4Byte3Full : 1; }; struct AmccInterruptControlStatus_register { Bit32 OutgoingMailBoxByte : 2; Bit32 OutgoingMailBoxWord : 2; // minus one Bit32 EnableOutgoingMailBoxGoesEmptyInterrupt : 1; Bit32 Reserved1 : 3; // must be zero Bit32 IncomingMailBoxByte : 2; Bit32 IncomingMailBoxWord : 2; // minus one Bit32 EnableIncomingMailBoxGoesFullInterrupt : 1; Bit32 Reserved2 : 1; // must be zero Bit32 EnableWriteTransferCompleteInterrupt : 1; Bit32 EnableReadTransferCompleteInterrupt : 1; // write one to clear // Bit32 OutgoingMailBoxInterrupted : 1; // write one to clear // Bit32 IncomingMailBoxInterrupted : 1; // write one to clear // Bit32 WriteTransferCompleted : 1; // write one to clear // Bit32 ReadTransferCompleted : 1; // write one to clear // Bit32 MasterAborted : 1; // write one to clear // Bit32 TargetAborted : 1; Bit32 Reserved3 : 1; // read only // // same as: // ReadTransferCompleted // OR WriteTransferCompleted // OR IncomingMailBoxInterrupted // OR OutgoingMailBoxInterrupted // Bit32 Interrupted : 1; // defaults to zero (NoConversion) // Bit32 EndianConversion : 2; // defaults to zero // Bit32 ReadFifoAdvanceByte : 2; // defaults to zero // Bit32 WriteFifoAdvanceByte : 2; // defaults to zero // // toggles after each 32-bit load // // if 1, EndianConversion must == Convert64Bits // Bit32 ReadFifoLoadedHigh32Of64Bits : 1; // defaults to zero // // toggles after each 32-bit load // // if 1, EndianConversion must == Convert64Bits // Bit32 WriteFifoLoadedHigh32Of64Bits : 1; }; enum AmccEndianConversion { NoConversion = 0, Convert16Bits, Convert32Bits, Convert64Bits }; // for 24C16 serial 8-pin 2Kx8 device // #define MAX_NVRAM_ADDRESS 2047 struct AmccBusMasterControlStatus_register { // read only // Bit32 ReadFifoFull : 1; // read only // Bit32 ReadFifo4WordsEmpty : 1; // read only // Bit32 ReadFifoEmpty : 1; // read only // Bit32 WriteFifoFull : 1; // read only // Bit32 WriteFifo4WordsFilled : 1; // read only // Bit32 WriteFifoEmpty : 1; // read only // Bit32 ReadTransferCountZero : 1; // read only // Bit32 WriteTransferCountZero : 1; // legend: read write behavior // vs. vs. // write read // // 0 0 ???undefined??? // 0 1 write has priority // 1 0 read has priority // 1 1 read and write alternate // Bit32 WriteVersusReadPriority : 1; // when 1, write FIFO must have 4 or more words // in it for matchmaker to request PCI bus // // when 0, write FIFO must have 1 or more words // in it for matchmaker to request PCI bus // Bit32 WriteFifo4FilledForPciReq : 1; // must be 1 for PCI bus master writes to take place // // can set clear to 0 to disable an active transfer // (when the transfer count is nonzero) // Bit32 EnableWriteTransfer : 1; // must be zero // Bit32 Reserved1 : 1; // see WriteVersusReadPriority above for legend // Bit32 ReadVersusWritePriority : 1; // when 1, read FIFO must have 4 or more words // available for matchmaker to request PCI bus // // when 0, read FIFO must have 1 or more words // available for matchmaker to request PCI bus // Bit32 ReadFifo4AvailableForPciReq : 1; // must be 1 for PCI bus master reads to take place // // can set clear to 0 to disable an active transfer // (when the transfer count is nonzero) // Bit32 EnableReadTransfer : 1; // must be zero // Bit32 Reserved2 : 1; Bit32 NvramAddressOrData : 8; // 1 asserts reset pin of addon interface // 0 deasserts it // Bit32 AddonResetPin : 1; // write only // // causes ReadFifoFull = 0, ReadFifoEmpty = 1 // ReadFifo4WordsEmpty = 1 // Bit32 ResetReadFifoFlags : 1; // write only // // causes WriteFifoFull = 0, WriteFifoEmpty = 1 // ReadFifo4WordsFilled = 0 // Bit32 ResetWriteFifoFlags : 1; // write only // // causes all mailbox flags to become 0 // Bit32 ResetMailBoxFlags : 1; // must be zero // Bit32 Reserved3 : 1; // see enum AmccNvramAccessType for opcode mnemonics // Bit32 NvramAccessType : 2; // wait for this bit to read as 0, // then write as 1 along with an opcode in NvramAccessType // and an 8-bit value in NvramAddressOrData // // also write this bit as 0 if you // don’t want an nvRAM cycle to occur // Bit32 NvramBusy : 1; }; enum AmccNvramAccessType { LoadLowAddressByte = 0, LoadHighAddressByte, BeginWrite, BeginRead }; #define AMCC_BASE_ADDR_REG 0 // merged registers // // base address register 0 (the 1st one) in PCI // configuration space points to this structure // struct Amcc_registers { // PCI slave accesses from host // can be 8, 16, or 32 bits wide // Bit32 OutgoingMailBoxes[ 4 ]; // PCI slave accesses from host // can be 8, 16, or 32 bits wide // Bit32 IncomingMailBoxes[ 4 ]; // cannot do a slave burst to this address // // reading this address from host when no // data is available causes a hard lockup! // // should not be accessed during bus master transfers // Bit32 Fifo; // low 2 bits must be zero, // so the address is DWORD aligned // Bit32 MasterWriteAddress; // measured in bytes // // upper 6 bits must be zero, // so max value is 64 MB – 1 // Bit32 MasterWriteTransferCount; // low 2 bits must be zero // so the address is DWORD aligned // Bit32 MasterReadAddress; // measured in bytes // // upper 6 bits must be zero, // so max value is 64 MB – 1 // Bit32 MasterReadTransferCount; // read only // AmccMailBoxStatuses_register MailBoxStatuses; // also has FIFO control/status // AmccInterruptControlStatus_register InterruptControlStatus; AmccBusMasterControlStatus_register BusMasterControlStatus; }; #endif // not included yet